1. Field of the Invention
The present invention relates to a method for manufacturing a bipolar semiconductor device capable of improving the electric characteristic at the connection between an electrode made of a polycrystalline semiconductor thin film which is used in a transistor for a bipolar transistor integration circuit and a semiconductor region containing a high concentration of impurity which is formed in a single crystalline semiconductor substrate.
2. Description of the Prior Art
In the recent technology for silicon semiconductor bipolar device, it has been widely received that poly silicon (polycrystalline silicon) is used for a wiring material for forming a fine circuit and for a diffusion source for forming a shallow junction depth. Particularly, a use of a leading-out electrode composed of a poly silicon thin film is an essential technology for achieving an emitter region in a fine planer dimension suitable for high speed operation of the semiconductor bipolar device. (Poly silicon emitter technology)
The following three methods are representative for achieving the poly silicon emitter structure.
(1) A method for forming an emitter region by diffusing an impurity from a poly silicon film to be an electrode.
According to this method, after introducing an impurity into the poly silicon to be an electrode the emitter region is formed by diffusing the impurity from the poly silicon through a heat treatment.
For example, the emitter region having a shallow junction depth of 50 nano meter can be formed through a diffusion process of arsenic ions by heating the poly silicon thin film having arsenic ions in a dose amount of 1.times.10.sup.16 cm.sup.-2 implanted therein at a temperature of 900.degree. for 30 min. A diffusion process of arsenic ions with the same poly silicon thin film as that of the above is carried out at a temperature of 1000.degree. C. for 20 min. The result is to form an emitter region having a junction depth of 180 nano meter superior in the high speed operation. However, such a deep junction depth requires a diffusion process carried out at a high temperature and for a long heating time, which affects undesirably other semiconductor regions such as a base region formed at the foregoing step. That is, the base region is provided with a deeper junction depth which prevents a high speed operation. In other words, a heat treatment at a temperature of 1000.degree. C. for 20 min. can achieve the formation of the emitter region having a deep junction depth of 180 nano meter and ensure the high speed operation of the resultant device. On the other hand, such a heat treatment has a disadvantage that the base region is provided with a deeper junction depth of 400 to 500 nano meter by the further diffusion of boron ions. This problem becomes more serious when the minimum dimension of an emitter diffusion window is 1 .mu.m or less since it becomes difficult to diffuse the impurity for forming an emitter therethrough.
When a p-type base region is formed with an implantation apparatus having the most stable and the lowest acceleration energy commercially available (for example, 25 keV), the heat treatment for obtaining the emitter region having a junction depth of 180 nano meter which results in a superior high speed operation (1000.degree. C. and 20 min.) causes the base region to have a junction depth of 500 nano meter. As a result of a difference between the junction depths of base region (500 nano meter) and the emitter (180 nano meter), the resultant transistor has a base width of 320 nano meter. A transistor with a base width of 320 nano meter is provided and typically has a collector cut-off frequency (ft) of 5 GHz. It is necessary for a transistor to be formed with a base region having a small base with such as 100 to 200 nano meter for easy manufacturing of a transistor of a high quality having a collector cut-off frequency (ft=10 GHz). In this case, the emitter region formed through a diffusion process from the poly silicon has a junction depth of 300 nano meter. The formation of an emitter with a deeper junction depth requires a heat treatment characterized by a high temperature and a long heating time. Under such a heat treatment, the base region is unwillingly provided with a considerably deep junction. As a result, it is impossible to achieve the formation of a transistor having a base width in a low level of about 100 to 200 nano meter.
(2) A method for depositing a poly silicon thin film after formation of an emitter region by ion implantation.
An emitter region according to this method is formed by implanting directly an impurity such as arsenic ions into a p-type base region. For example, a substrate has arsenic ions in a dose amount of 1.times.10.sup.16 cm.sup.-2 implanted thereunto with an acceleration energy of 50 keV and then heated at a temperature of 1000.degree. C. The emitter region has a junction depth of about 100 nano meter after implantation and then of 260 nano meter after heating of 20 min. In the emitter formation method according to the method (1), the emitter region has a junction depth of about 180 nano meter after a diffusion of arsenic ions from the poly silicon carried out at a temperature of 1000.degree. C. for 20 min. The emitter region according to the method (2) has a junction depth of 260 nano meter upon being subjected to the same heat treatment, that is (1000.degree. C., 20 min.) which is larger by 80 nano meter than that of the emitter formed according to the method (1). The amount of implanted arsenic ions is higher with the method (2) than with the method (1). The higher amount of arsenic ions preferably causes the emitter to have a lower electric resistance. However, the implantation of an impurity such as arsenic ions causes the p-type base to have a rough surface. A silicon oxide thin film (referred to as a "native oxide film" hereinafter) is spontaneously formed between a substrate of a single crystal silicon and a poly silicon thin film for use in a leading-out electrode. The rough surface of the substrate causes the native oxide film to grow irregularly. The variation in the thickness of the native oxide film results in an undesirable increase in the serial electrical resistance at the emitter region.
(3) A method for forming an emitter region by implanting an impurity through a polycrystalline semiconductor thin film such as poly silicon.
This method forms an emitter region by implanting an impurity such as arsenic ions of an n-type into a base of a p-type through a thin film of poly silicon. An emitter region according to a method (3) is formed by implanting an impurity such as arsenic into a silicon substrate with an acceleration energy of 70 keV (higher by 20 keV than that of the method (2)) and is provided with an impurity distribution the same as that of method (2). In addition, the higher acceleration energy according to the method (3) can break the native oxide film formed between the substrate of a single crystal silicon and the poly silicon thin film and accordingly improve the ohmic contact between the semiconductor thin film to be a leading-out electrode and the emitter region. This results in a decrease in the serial electric resistance at the emitter region. Since it becomes difficult to remove the native oxide film before depositing a non-single crystalline thin film as the size of an emitter diffusion window is miniaturized, variety in the electric property among transistors formed in the same wafer or among wafers in the same batch increases undesirably.
A first problem to be solved by the invention is to remove an undesirable effect due to the native oxide film formed between a silicon substrate of a single crystal form and the poly silicon. This native oxide film grows up to a thickness of 2 nano meter with the poly silicon film or amorphous silicon thin film as deposited. The increase in the thickness of this native oxide film causes the diffusion length of an impurity in an emitter region, that is, the junction depth to be irregularly lower or higher, and further results in an increase in the serial electrical resistance of the resultant emitter region. Accordingly, there have been problems that degrade the transistor characteristic and that increase the variation of the properties.
This problem further increases the difficulty in leading-out an electrode film of a poly silicon or amorphous silicon from an emitter region after formation of an emitter having a deep junction through an ion implantation process according to the emitter formation method shown in the method (2). As mentioned above, the native oxide film grows between the substrate of a single crystal silicon and the poly silicon film. The growth rate is higher with the substrate including a higher concentration of impurity such as arsenic ions than with the substrate including a lower concentration of impurity. As a result, the substrate including a higher concentration of impurity degrades the ohmic contact between the emitter region and the deposited poly silicon thin film and results in a rapid increase in the serial electric resistance of the emitter region.
A second problem of the present invention is to form the junction at a considerably greater depth with a heat treatment at lower temperature and for a short heating time. When an emitter having a junction in a given depth can be formed through a heat treatment at a lower temperature for the short heating time, it is possible to achieve a transistor structure having a narrow base width superior in the high speed operation without changing the profile of an impurity of the base. For example, the formation of the emitter having the junction depth of 300 nano meter requires a heat treatment at a temperature of 1000.degree. C. for 60 min., which causes the base region formed at the foregoing step to have the impurity diffused further thereunto. Accordingly, this has been a problem preventing the achievement of the transistor structure suitable for high speed operation.
In the method (3) according to the prior art, an emitter region is formed by implanting the impurity ions into a p-type base region through a semiconductor thin film of a non-single crystal form such as a poly crystal silicon or an amorphous silicon. A variation in the thickness of a polycrystalline semiconductor thin film form affects undesirably the junction depth of the emitter region. Accordingly, this causes a variation in the base width which is a difference between the junction depths of an emitter and the junction depth of the base region formed with the ion implantation process at the foregoing step. The resultant transistors have a variation in the electric characteristic.